History: usbd_drv_arc
This page describes all changes made to the usbd_drv_arc package, USBD Low Level Driver for ARC, since its release.
Version
1.14 (2019-09-13, 12:00):
- Eliminated C++ compiler errors.
1.13r2 (2018-08-29, 18:22):
- Document HTML link added to the documentation folder.
- History and document files renamed to the package name.
1.13 (2017-10-10, 16:12):
- Fixed problem that meant fast connect-disconnect (plugging the cable in and out) could result in the driver getting stuck.
1.12r3 (2017-10-03, 22:13):
- Added PSP template for Zynq 7000.
1.12r2 (2017-07-05, 14:25):
- Added PSP template for TWR-K65F180M development board.
1.12:
- Cable removal or USB reset issued by host during active transfers could lead to undefined behavior in rare cases.
1.11:
- The stack could interpret SETUP packet in case those were sent very quickly by the host.
- Zero length packet generation was enabled causing incorrect operation for class driver where ZLP is not required (e.g. mass storage).
- Memory could slowly consumed if a SETUP packet was sent during the data phase as the driver was not able to identify the interrupted transfer correctly.
- Added OAL_TASK_PRE macro to transfer task.
1.10:
- Added USB device test mode.
1.9:
- Corrected transfer task to work in poll mode.
1.8:
- Typo fixed.
1.7:
- Corrected bug, where bremain was not initialized to 0 in usb_dtd_length so in some cases TX transfers were ended as short packet before all bytes are sent.
- hcc_mem_unlock() is called in usbd_dtd_length() instead of hcc_mem_unlock_int() in case of transfer task is used.
1.6:
- Uninitialized variables in usbd_hw_init() fixed.
- Configuration file reorganized.
1.5:
- Introduced USBD_USE_TFR_TASK to use data memcpy in a task, to prevent high interrupt load.
- Used hcc_mem_lock_tr instead of hcc_mem_lock.
- Updated init and delete functions.
- Introduced bremain flag for transfers to indicate remaining data bytes.
1.4:
- General cleanup.
1.3:
- In case of HCC_MEM_ALLOW_DATA_CACHE == 0 hcc_mem_lock() function is only called if necessary. For example when the HW is not able to do DMA transfers from flash area.
1.2:
- warnings removed.
- VBUS interrupt fixed.
1.1:
- register and structure access reverse endianness handling separated.
- virtual/physical memory address usage fixed.
- commented.
1.0:
- Initial release.